1. Field of the Invention
The present invention relates to a thin film transistor (TFT) for a display device, and more particularly, to a method of fabricating a bottom-gated polycrystalline silicon TFT.
2. Discussion of the Related Art
In general, TFTs are used as switching elements for liquid crystal display (LCD) devices. Of the different types of LCD devices, active matrix LCD (AM-LCD) devices are used because of their high resolution and superiority in displaying moving images. An LCD device includes two substrates disposed such that respective electrodes of the two substrates face into each other, and a liquid crystal layer is interposed between the respective electrodes. When a voltage is supplied to the electrodes, an electric field is induced to the liquid crystal layer, thereby modulating light transmittance of the liquid crystal layer by reorienting liquid crystal molecules of the liquid crystal layer to display images.
FIG. 1 is a schematic perspective view of a liquid crystal display device according to the related art. In FIG. 1, first and second substrates 10 and 30 face and are spaced apart from each other, wherein a plurality of gate lines 12 and a plurality of data lines 14 are formed on an inner surface of the first substrate 10 to cross each other. Accordingly, a pixel region “P” is defined by the crossings of the gate line 12 and the data line 14, and a pixel electrode 16 is formed in the pixel region “P.” In addition, a TFT “T” is connected to the gate line 12 and the data line 14, and a color filter layer 32 and a common electrode 34 are sequentially formed on an inner surface of the second substrate 30. The color filter layer 32 transmits only light having a specific wavelength range. A liquid crystal layer 50 is interposed between the pixel electrode 16 and the common electrode 34, and first and second polarizing plates 52 and 54 are disposed along exterior surfaces of the first and second substrates 10 and 30, respectively. In addition, a backlight unit is disposed outside the first polarizing plate 52 to function as a light source.
In FIG. 1, the TFT “T” is used as a switching element turning ON/OFF to provide a voltage transmitted along the data line 14 to the pixel electrode 16. Accordingly, the TFT “T” determines display characteristics of the LCD device.
FIGS. 2A to 2I are schematic cross sectional views of a method of fabricating a thin film transistor for a liquid crystal display device according to the related art. In FIGS. 2A to 2I, a bottom-gated type thin film transistor is shown. Since a gate insulating layer, an amorphous silicon layer, and an impurity-doped amorphous silicon layer are sequentially formed in a vacuum chamber, the bottom-gated type thin film transistor has excellent electric properties and simplified fabricating processes.
In FIG. 2A, a first metal layer 72 is formed on a substrate 70.
In FIG. 2B, a first photoresist (PR) pattern 74 is formed on the first metal layer 72 through photolithographic processes. Although not shown in FIG. 2B, the photolithographic processes for forming the first PR pattern 74 includes steps of forming a PR layer on the first metal layer 72, disposing a mask having an open portion over the PR layer, exposing the PR layer through the mask and developing the exposed PR layer.
In FIG. 2C, the first metal layer 72 is etched using the first PR pattern 74 as an etching mask. Then, the PR pattern 74 is removed to form a gate electrode 76.
In FIG. 2D, a gate insulating layer 78, an intrinsic amorphous silicon layer 80, and an impurity-doped amorphous silicon layer 82 are sequentially formed on the gate electrode 76.
In FIG. 2E, a second PR pattern 84 is formed on the impurity-doped amorphous silicon layer 82. The second PR pattern 84 may be formed through photolithographic processes similar to processes used for the first PR pattern 74 (in FIG. 2B).
In FIG. 2F, the impurity-doped amorphous silicon layer 82 and the intrinsic amorphous silicon layer 80 are etched using the second PR pattern 84 as an etching mask to form a semiconductor layer 86 corresponding to the second PR pattern 84. The semiconductor layer 86 includes an active layer 86a of the etched intrinsic amorphous silicon layer 80 and an ohmic contact layer 86b of the etched impurity-doped amorphous silicon layer 82.
In FIG. 2G, a second metal layer 88 is formed on the semiconductor layer 86.
In FIG. 2H, third PR patterns 90a and 90b are formed on the second metal layer 88 over the semiconductor layer 86. The third PR patterns 90a and 90b are spaced apart from each other.
In FIG. 21, source and drain electrodes 92 and 94 corresponding to the third PR patterns 90a and 90b are formed by etching the second metal layer 88 using the third PR patterns 90a and 90b as an etching mask. The ohmic contact layer 86b exposed between the source and drain electrodes 92 and 94 is removed using the source and drain electrodes 92 and 94 as an etching mask, thereby exposing a channel region “ch” of the active layer 86a. The gate electrode 76, the semiconductor layer 86, the source electrode 92, and the drain electrode 94 constitute a thin film transistor (TFT) “T.”
According to the related art, a patterning process for a semiconductor layer of a bottom-gated type amorphous silicon TFT includes steps of coating a PR layer, exposing the PR layer, and developing the exposed PR layer. Accordingly, each individual fabrication process and process time increases production costs and reduces production yield.